Parallel High-Order Integrators

In this work we discuss a class of defect correction methods which is easily adapted to create parallel time integrators for multi-core architectures and is ideally suited for developing methods which can be order adaptive in time. The method is based on Integral Deferred Correction (IDC), which was itself motivated by Spectral Deferred Correction by Dutt, Greengard and Rokhlin (BIT-2000). The method presented here is a revised formulation of explicit IDC, dubbed Revisionist IDC, which can achieve pth-order accuracy in “wall-clock time” comparable to a single forward Euler simulation on problems where the time to evaluate the right-hand side of a system of differential equations is greater than latency costs of inter-processor communication, such as in the case of the N -body problem. The key idea is to re-write the defect correction framework so that, after initial startup costs, each correction loop can be lagged behind the previous correction loop in a manner that facilitates running the predictor and M = p−1 correctors in parallel on an interval which has K steps, where K p. We prove that given an rth-order Runge–Kutta method in both the prediction and M correction loops of RIDC, then the method is order r × (M + 1). The parallelization in Revisionist IDC uses a small number of cores (the number of processors used is limited by the order one wants to achieve). Using a four-core CPU, it is natural to think about fourth-order RIDC built with forward Euler, or eighth-order RIDC constructed with secondorder Runge–Kutta. Numerical tests on an N -body simulation show that RIDC methods can be significantly faster than popular Runge–Kutta methods such as the classical fourth-order Runge– Kutta scheme. In a PDE setting, one can imagine coupling RIDC time integrators with parallel spatial evaluators, thereby increasing the parallelization. The ideas behind RIDC extend to implicit and semiimplicit IDC and have high potential in this area.